1#include "mspm0_i2c.hpp"
3#include <ti/driverlib/dl_dma.h>
13constexpr uint32_t MSPM0_I2C_WAIT_IDLE_TIMEOUT = 300000;
14constexpr uint32_t MSPM0_I2C_WAIT_BUS_TIMEOUT = 300000;
15constexpr uint32_t MSPM0_I2C_WAIT_FIFO_TIMEOUT = 300000;
16constexpr uint32_t MSPM0_I2C_POLLING_ATTEMPTS = 2;
17constexpr uint32_t MSPM0_I2C_MEMREAD_RS_ATTEMPTS = 2;
18constexpr uint32_t MSPM0_I2C_MEMREAD_FALLBACK_ATTEMPTS = 3;
20constexpr uint16_t MSPM0_I2C_MAX_TRANSFER_SIZE = 0x0FFF;
24#if defined(DMA_CH_TX_CHAN_ID) != defined(DMA_CH_RX_CHAN_ID)
25#error "MSPM0I2C requires both TX and RX DMA bindings, or neither."
27#if defined(DMA_CH_TX_CHAN_ID) && defined(DMA_CH_RX_CHAN_ID)
28constexpr bool I2C_DMA_CONFIGURED =
true;
29constexpr uint8_t I2C_DMA_TX_CHANNEL = DMA_CH_TX_CHAN_ID;
30constexpr uint8_t I2C_DMA_RX_CHANNEL = DMA_CH_RX_CHAN_ID;
31static_assert(DMA_CH_TX_CHAN_ID < DMA_SYS_N_DMA_CHANNEL);
32static_assert(DMA_CH_RX_CHAN_ID < DMA_SYS_N_DMA_CHANNEL);
33static_assert(DMA_CH_TX_CHAN_ID != DMA_CH_RX_CHAN_ID);
35constexpr bool I2C_DMA_CONFIGURED =
false;
37constexpr uint8_t I2C_DMA_TX_CHANNEL = 0U;
38constexpr uint8_t I2C_DMA_RX_CHANNEL = 0U;
41constexpr DL_DMA_Config MSPM0_I2C_DMA_TX_CONFIG_BASE = {
43 .triggerType = DL_DMA_TRIGGER_TYPE_EXTERNAL,
44 .transferMode = DL_DMA_SINGLE_TRANSFER_MODE,
45 .extendedMode = DL_DMA_NORMAL_MODE,
46 .srcWidth = DL_DMA_WIDTH_BYTE,
47 .destWidth = DL_DMA_WIDTH_BYTE,
48 .srcIncrement = DL_DMA_ADDR_INCREMENT,
49 .destIncrement = DL_DMA_ADDR_UNCHANGED,
52constexpr DL_DMA_Config MSPM0_I2C_DMA_RX_CONFIG_BASE = {
54 .triggerType = DL_DMA_TRIGGER_TYPE_EXTERNAL,
55 .transferMode = DL_DMA_SINGLE_TRANSFER_MODE,
56 .extendedMode = DL_DMA_NORMAL_MODE,
57 .srcWidth = DL_DMA_WIDTH_BYTE,
58 .destWidth = DL_DMA_WIDTH_BYTE,
59 .srcIncrement = DL_DMA_ADDR_UNCHANGED,
60 .destIncrement = DL_DMA_ADDR_INCREMENT,
63constexpr uint32_t mspm0_i2c_dma_channel_mask(uint8_t channel_id)
65 return (1UL << channel_id);
68bool mspm0_i2c_resolve_dma_triggers(I2C_Regs* instance, uint8_t& tx_trigger,
71#if defined(I2C0_BASE) && defined(DMA_I2C0_TX_TRIG) && defined(DMA_I2C0_RX_TRIG)
74 tx_trigger = DMA_I2C0_TX_TRIG;
75 rx_trigger = DMA_I2C0_RX_TRIG;
79#if defined(I2C1_BASE) && defined(DMA_I2C1_TX_TRIG) && defined(DMA_I2C1_RX_TRIG)
82 tx_trigger = DMA_I2C1_TX_TRIG;
83 rx_trigger = DMA_I2C1_RX_TRIG;
87#if defined(I2C2_BASE) && defined(DMA_I2C2_TX_TRIG) && defined(DMA_I2C2_RX_TRIG)
90 tx_trigger = DMA_I2C2_TX_TRIG;
91 rx_trigger = DMA_I2C2_RX_TRIG;
95#if defined(I2C3_BASE) && defined(DMA_I2C3_TX_TRIG) && defined(DMA_I2C3_RX_TRIG)
98 tx_trigger = DMA_I2C3_TX_TRIG;
99 rx_trigger = DMA_I2C3_RX_TRIG;
106constexpr bool mspm0_i2c_is_valid_addr7(uint16_t slave_addr)
108 return slave_addr <= 0x7FU;
111void mspm0_i2c_recover_controller(I2C_Regs* instance)
113 DL_I2C_disableInterrupt(instance, 0xFFFFFFFFU);
114 DL_I2C_clearInterruptStatus(instance, 0xFFFFFFFFU);
115 DL_I2C_disableControllerReadOnTXEmpty(instance);
116 DL_I2C_resetControllerTransfer(instance);
117 DL_I2C_enableController(instance);
122MSPM0I2C::MSPM0I2C(Resources res,
RawData stage_buffer, uint32_t dma_enable_min_size,
126 stage_buffer_(stage_buffer),
127 dma_enable_min_size_(dma_enable_min_size)
129 ASSERT(res_.instance !=
nullptr);
130 ASSERT(res_.clock_freq > 0);
131 ASSERT(res_.index < MAX_I2C_INSTANCES);
132 ASSERT(stage_buffer_.addr_ !=
nullptr);
133 ASSERT(stage_buffer_.size_ > 0);
139 const ErrorCode SET_CFG_ANS = SetConfig(config);
140 REQUIRE(SET_CFG_ANS == ErrorCode::OK);
143ErrorCode MSPM0I2C::CheckControllerError()
const
145 const uint32_t STATUS = DL_I2C_getControllerStatus(res_.instance);
146 if ((STATUS & DL_I2C_CONTROLLER_STATUS_ERROR) != 0 ||
147 (STATUS & DL_I2C_CONTROLLER_STATUS_ARBITRATION_LOST) != 0)
154ErrorCode MSPM0I2C::WaitControllerIdle()
const
156 uint32_t timeout = MSPM0_I2C_WAIT_IDLE_TIMEOUT;
157 while (timeout-- > 0)
159 if ((DL_I2C_getControllerStatus(res_.instance) & DL_I2C_CONTROLLER_STATUS_IDLE) != 0)
171ErrorCode MSPM0I2C::WaitTransactionDone()
const
173 uint32_t timeout = MSPM0_I2C_WAIT_FIFO_TIMEOUT;
174 while (timeout-- > 0)
176 if (DL_I2C_getTransactionCount(res_.instance) == 0)
190 uint32_t timeout = MSPM0_I2C_WAIT_BUS_TIMEOUT;
191 while (timeout-- > 0)
193 if ((DL_I2C_getControllerStatus(res_.instance) & DL_I2C_CONTROLLER_STATUS_BUSY_BUS) ==
208 if (res_.instance ==
nullptr || res_.clock_freq == 0U || config.
clock_speed == 0U)
218 const uint64_t PERIOD_DEN = uint64_t(config.
clock_speed) * 10U;
219 const uint64_t period_factor =
220 (uint64_t(res_.clock_freq) + PERIOD_DEN - 1U) / PERIOD_DEN;
221 if (period_factor == 0)
225 if (period_factor > 128U)
230 if ((DL_I2C_getControllerStatus(res_.instance) &
231 (DL_I2C_CONTROLLER_STATUS_BUSY | DL_I2C_CONTROLLER_STATUS_BUSY_BUS)) != 0U)
236 const uint8_t TIMER_PERIOD =
static_cast<uint8_t
>(period_factor - 1U);
237 const DL_I2C_ClockConfig CLOCK_CONFIG = {
238 .clockSel = DL_I2C_CLOCK_BUSCLK,
239 .divideRatio = DL_I2C_CLOCK_DIVIDE_1,
242 uint8_t dma_tx_trigger = 0U;
243 uint8_t dma_rx_trigger = 0U;
245 I2C_DMA_CONFIGURED &&
246 mspm0_i2c_resolve_dma_triggers(res_.instance, dma_tx_trigger, dma_rx_trigger);
247 dma_enabled_ = USE_DMA;
249 DL_I2C_disableController(res_.instance);
250 DL_I2C_setClockConfig(res_.instance, &CLOCK_CONFIG);
251 DL_I2C_resetControllerTransfer(res_.instance);
252 DL_I2C_setTimerPeriod(res_.instance, TIMER_PERIOD);
253 DL_I2C_setControllerTXFIFOThreshold(
254 res_.instance, USE_DMA ? DL_I2C_TX_FIFO_LEVEL_EMPTY : DL_I2C_TX_FIFO_LEVEL_BYTES_1);
255 DL_I2C_setControllerRXFIFOThreshold(res_.instance, DL_I2C_RX_FIFO_LEVEL_BYTES_1);
256 DL_I2C_enableControllerClockStretching(res_.instance);
257 DL_I2C_disableInterrupt(res_.instance, 0xFFFFFFFFU);
258 DL_I2C_clearInterruptStatus(res_.instance, 0xFFFFFFFFU);
260 DL_I2C_disableDMAEvent(res_.instance, DL_I2C_EVENT_ROUTE_1,
261 DL_I2C_DMA_INTERRUPT_CONTROLLER_TXFIFO_TRIGGER);
262 DL_I2C_disableDMAEvent(res_.instance, DL_I2C_EVENT_ROUTE_2,
263 DL_I2C_DMA_INTERRUPT_CONTROLLER_RXFIFO_TRIGGER);
266 DL_DMA_disableChannel(DMA, I2C_DMA_TX_CHANNEL);
267 DL_DMA_disableChannel(DMA, I2C_DMA_RX_CHANNEL);
268 DL_DMA_clearInterruptStatus(DMA, mspm0_i2c_dma_channel_mask(I2C_DMA_TX_CHANNEL) |
269 mspm0_i2c_dma_channel_mask(I2C_DMA_RX_CHANNEL));
274 DL_DMA_Config dma_tx_config = MSPM0_I2C_DMA_TX_CONFIG_BASE;
275 DL_DMA_Config dma_rx_config = MSPM0_I2C_DMA_RX_CONFIG_BASE;
276 dma_tx_config.trigger = dma_tx_trigger;
277 dma_rx_config.trigger = dma_rx_trigger;
279 DL_I2C_enableDMAEvent(res_.instance, DL_I2C_EVENT_ROUTE_1,
280 DL_I2C_DMA_INTERRUPT_CONTROLLER_TXFIFO_TRIGGER);
281 DL_I2C_enableDMAEvent(res_.instance, DL_I2C_EVENT_ROUTE_2,
282 DL_I2C_DMA_INTERRUPT_CONTROLLER_RXFIFO_TRIGGER);
283 DL_DMA_initChannel(DMA, I2C_DMA_TX_CHANNEL, &dma_tx_config);
284 DL_DMA_initChannel(DMA, I2C_DMA_RX_CHANNEL, &dma_rx_config);
287 DL_I2C_enableController(res_.instance);
292ErrorCode MSPM0I2C::PollingWrite7(uint16_t addr7,
const uint8_t* data,
size_t size)
298 if (size > MSPM0_I2C_MAX_TRANSFER_SIZE)
311 DL_I2C_clearInterruptStatus(res_.instance, 0xFFFFFFFFU);
314 DL_I2C_fillControllerTXFIFO(res_.instance, data,
static_cast<uint16_t
>(size));
315 DL_I2C_startControllerTransfer(res_.instance, addr7, DL_I2C_CONTROLLER_DIRECTION_TX,
316 static_cast<uint16_t
>(size));
320 uint32_t timeout = MSPM0_I2C_WAIT_FIFO_TIMEOUT;
321 while (DL_I2C_getRawInterruptStatus(
322 res_.instance, DL_I2C_INTERRUPT_CONTROLLER_TXFIFO_TRIGGER) == 0U)
334 sent += DL_I2C_fillControllerTXFIFO(res_.instance, data + sent,
335 static_cast<uint16_t
>(size - sent));
344 return CheckControllerError();
348 for (uint32_t attempt = 0; attempt < MSPM0_I2C_POLLING_ATTEMPTS; ++attempt)
350 last_error = attempt_once();
355 mspm0_i2c_recover_controller(res_.instance);
361ErrorCode MSPM0I2C::PollingRead7(uint16_t addr7, uint8_t* data,
size_t size)
367 if (size > MSPM0_I2C_MAX_TRANSFER_SIZE)
380 DL_I2C_clearInterruptStatus(res_.instance, 0xFFFFFFFFU);
381 DL_I2C_startControllerTransfer(res_.instance, addr7, DL_I2C_CONTROLLER_DIRECTION_RX,
382 static_cast<uint16_t
>(size));
385 while (received < size)
387 uint32_t timeout = MSPM0_I2C_WAIT_FIFO_TIMEOUT;
388 while (DL_I2C_isControllerRXFIFOEmpty(res_.instance))
400 while (!DL_I2C_isControllerRXFIFOEmpty(res_.instance) && received < size)
402 data[received++] = DL_I2C_receiveControllerData(res_.instance);
412 return CheckControllerError();
416 for (uint32_t attempt = 0; attempt < MSPM0_I2C_POLLING_ATTEMPTS; ++attempt)
418 last_error = attempt_once();
423 mspm0_i2c_recover_controller(res_.instance);
429ErrorCode MSPM0I2C::WaitDmaTransferDone(uint8_t channel_id)
const
431 uint32_t timeout = MSPM0_I2C_WAIT_FIFO_TIMEOUT;
432 while (DL_DMA_getTransferSize(DMA, channel_id) != 0U)
448 if (write_data.
size_ == 0)
452 if (write_data.
size_ > MSPM0_I2C_MAX_TRANSFER_SIZE)
457 auto stop_dma = [&]()
459 const uint32_t DMA_TX_MASK = mspm0_i2c_dma_channel_mask(I2C_DMA_TX_CHANNEL);
460 DL_DMA_disableChannel(DMA, I2C_DMA_TX_CHANNEL);
461 DL_DMA_clearInterruptStatus(DMA, DMA_TX_MASK);
472 DL_I2C_disableInterrupt(res_.instance, 0xFFFFFFFFU);
473 DL_I2C_clearInterruptStatus(res_.instance, 0xFFFFFFFFU);
475 const uint32_t DMA_TX_MASK = mspm0_i2c_dma_channel_mask(I2C_DMA_TX_CHANNEL);
476 DL_DMA_disableChannel(DMA, I2C_DMA_TX_CHANNEL);
477 DL_DMA_clearInterruptStatus(DMA, DMA_TX_MASK);
479 DMA, I2C_DMA_TX_CHANNEL,
480 static_cast<uint32_t
>(
reinterpret_cast<uintptr_t
>(write_data.
addr_)));
481 DL_DMA_setDestAddr(DMA, I2C_DMA_TX_CHANNEL,
482 static_cast<uint32_t
>(
483 reinterpret_cast<uintptr_t
>(&res_.instance->MASTER.MTXDATA)));
484 DL_DMA_setTransferSize(DMA, I2C_DMA_TX_CHANNEL,
485 static_cast<uint16_t
>(write_data.
size_));
486 DL_DMA_enableChannel(DMA, I2C_DMA_TX_CHANNEL);
488 DL_I2C_startControllerTransfer(res_.instance, addr7, DL_I2C_CONTROLLER_DIRECTION_TX,
489 static_cast<uint16_t
>(write_data.
size_));
491 ans = WaitDmaTransferDone(I2C_DMA_TX_CHANNEL);
498 ans = WaitTransactionDone();
513 return CheckControllerError();
517 for (uint32_t attempt = 0; attempt < MSPM0_I2C_POLLING_ATTEMPTS; ++attempt)
519 last_error = attempt_once();
524 mspm0_i2c_recover_controller(res_.instance);
532 if (read_data.
size_ == 0)
536 if (read_data.
size_ > MSPM0_I2C_MAX_TRANSFER_SIZE)
541 auto stop_dma = [&]()
543 const uint32_t DMA_RX_MASK = mspm0_i2c_dma_channel_mask(I2C_DMA_RX_CHANNEL);
544 DL_DMA_disableChannel(DMA, I2C_DMA_RX_CHANNEL);
545 DL_DMA_clearInterruptStatus(DMA, DMA_RX_MASK);
556 DL_I2C_disableInterrupt(res_.instance, 0xFFFFFFFFU);
557 DL_I2C_clearInterruptStatus(res_.instance, 0xFFFFFFFFU);
559 const uint32_t DMA_RX_MASK = mspm0_i2c_dma_channel_mask(I2C_DMA_RX_CHANNEL);
560 DL_DMA_disableChannel(DMA, I2C_DMA_RX_CHANNEL);
561 DL_DMA_clearInterruptStatus(DMA, DMA_RX_MASK);
562 DL_DMA_setSrcAddr(DMA, I2C_DMA_RX_CHANNEL,
563 static_cast<uint32_t
>(
564 reinterpret_cast<uintptr_t
>(&res_.instance->MASTER.MRXDATA)));
566 DMA, I2C_DMA_RX_CHANNEL,
567 static_cast<uint32_t
>(
reinterpret_cast<uintptr_t
>(read_data.
addr_)));
568 DL_DMA_setTransferSize(DMA, I2C_DMA_RX_CHANNEL,
569 static_cast<uint16_t
>(read_data.
size_));
570 DL_DMA_enableChannel(DMA, I2C_DMA_RX_CHANNEL);
572 DL_I2C_startControllerTransfer(res_.instance, addr7, DL_I2C_CONTROLLER_DIRECTION_RX,
573 static_cast<uint16_t
>(read_data.
size_));
575 ans = WaitDmaTransferDone(I2C_DMA_RX_CHANNEL);
582 ans = WaitTransactionDone();
597 return CheckControllerError();
601 for (uint32_t attempt = 0; attempt < MSPM0_I2C_POLLING_ATTEMPTS; ++attempt)
603 last_error = attempt_once();
608 mspm0_i2c_recover_controller(res_.instance);
617 if (read_data.
size_ == 0)
619 if (op.
type != ReadOperation::OperationType::BLOCK)
626 if (!mspm0_i2c_is_valid_addr7(slave_addr))
628 if (op.
type != ReadOperation::OperationType::BLOCK)
635 const uint16_t ADDR7 = slave_addr;
637 if (dma_enabled_ && read_data.
size_ > dma_enable_min_size_)
639 ans = DmaRead7(ADDR7, read_data);
643 ans = PollingRead7(ADDR7,
static_cast<uint8_t*
>(read_data.
addr_), read_data.
size_);
646 if (op.
type != ReadOperation::OperationType::BLOCK)
656 if (write_data.
size_ == 0)
658 if (op.
type != WriteOperation::OperationType::BLOCK)
665 if (!mspm0_i2c_is_valid_addr7(slave_addr))
667 if (op.
type != WriteOperation::OperationType::BLOCK)
674 const uint16_t ADDR7 = slave_addr;
676 if (dma_enabled_ && write_data.
size_ > dma_enable_min_size_)
678 ans = DmaWrite7(ADDR7, write_data);
682 ans = PollingWrite7(ADDR7,
static_cast<const uint8_t*
>(write_data.
addr_),
686 if (op.
type != WriteOperation::OperationType::BLOCK)
695 MemAddrLength mem_addr_size,
bool in_isr)
697 if (!mspm0_i2c_is_valid_addr7(slave_addr))
699 if (op.
type != WriteOperation::OperationType::BLOCK)
705 const size_t ADDR_SIZE = (mem_addr_size == MemAddrLength::BYTE_8) ? 1 : 2;
706 const size_t TOTAL_SIZE = ADDR_SIZE + write_data.
size_;
707 if (TOTAL_SIZE > MSPM0_I2C_MAX_TRANSFER_SIZE)
711 if (TOTAL_SIZE > stage_buffer_.
size_)
716 auto* tx =
static_cast<uint8_t*
>(stage_buffer_.
addr_);
719 tx[0] =
static_cast<uint8_t
>(mem_addr & 0xFF);
723 tx[0] =
static_cast<uint8_t
>((mem_addr >> 8) & 0xFF);
724 tx[1] =
static_cast<uint8_t
>(mem_addr & 0xFF);
726 if (write_data.
size_ > 0)
728 memcpy(tx + ADDR_SIZE, write_data.
addr_, write_data.
size_);
737 if (read_data.
size_ > MSPM0_I2C_MAX_TRANSFER_SIZE)
741 if (read_data.
size_ == 0)
743 if (op.
type != ReadOperation::OperationType::BLOCK)
750 if (!mspm0_i2c_is_valid_addr7(slave_addr))
752 if (op.
type != ReadOperation::OperationType::BLOCK)
759 const uint16_t ADDR7 = slave_addr;
760 const size_t ADDR_SIZE = (mem_addr_size == MemAddrLength::BYTE_8) ? 1 : 2;
761 auto* addr_bytes =
static_cast<uint8_t*
>(stage_buffer_.
addr_);
762 if (stage_buffer_.
size_ < ADDR_SIZE)
769 addr_bytes[0] =
static_cast<uint8_t
>(mem_addr & 0xFF);
773 addr_bytes[0] =
static_cast<uint8_t
>((mem_addr >> 8) & 0xFF);
774 addr_bytes[1] =
static_cast<uint8_t
>(mem_addr & 0xFF);
779 if (op.
type != ReadOperation::OperationType::BLOCK)
786 auto try_repeated_start = [&]() ->
ErrorCode
794 DL_I2C_clearInterruptStatus(res_.instance, 0xFFFFFFFFU);
796 const uint16_t ADDR_SENT = DL_I2C_fillControllerTXFIFO(
797 res_.instance, addr_bytes,
static_cast<uint16_t
>(ADDR_SIZE));
798 if (ADDR_SENT != ADDR_SIZE)
803 DL_I2C_startControllerTransferAdvanced(
804 res_.instance, ADDR7, DL_I2C_CONTROLLER_DIRECTION_TX,
805 static_cast<uint16_t
>(ADDR_SIZE), DL_I2C_CONTROLLER_START_ENABLE,
806 DL_I2C_CONTROLLER_STOP_DISABLE, DL_I2C_CONTROLLER_ACK_ENABLE);
808 uint32_t tx_done_timeout = MSPM0_I2C_WAIT_FIFO_TIMEOUT;
809 while (DL_I2C_getRawInterruptStatus(res_.instance,
810 DL_I2C_INTERRUPT_CONTROLLER_TX_DONE) == 0U)
816 if (tx_done_timeout-- == 0U)
821 DL_I2C_clearInterruptStatus(res_.instance, DL_I2C_INTERRUPT_CONTROLLER_TX_DONE);
828 DL_I2C_startControllerTransferAdvanced(
829 res_.instance, ADDR7, DL_I2C_CONTROLLER_DIRECTION_RX,
830 static_cast<uint16_t
>(read_data.
size_), DL_I2C_CONTROLLER_START_ENABLE,
831 DL_I2C_CONTROLLER_STOP_ENABLE, DL_I2C_CONTROLLER_ACK_DISABLE);
834 auto* read_ptr =
static_cast<uint8_t*
>(read_data.
addr_);
835 while (received < read_data.
size_)
837 uint32_t timeout = MSPM0_I2C_WAIT_FIFO_TIMEOUT;
838 while (DL_I2C_isControllerRXFIFOEmpty(res_.instance))
850 while (!DL_I2C_isControllerRXFIFOEmpty(res_.instance) && received < read_data.
size_)
852 read_ptr[received++] = DL_I2C_receiveControllerData(res_.instance);
856 uint32_t rx_done_timeout = MSPM0_I2C_WAIT_FIFO_TIMEOUT;
857 while (DL_I2C_getRawInterruptStatus(res_.instance,
858 DL_I2C_INTERRUPT_CONTROLLER_RX_DONE) == 0U)
864 if (rx_done_timeout-- == 0U)
869 DL_I2C_clearInterruptStatus(res_.instance, DL_I2C_INTERRUPT_CONTROLLER_RX_DONE);
877 return CheckControllerError();
881 for (uint32_t attempt = 0; attempt < MSPM0_I2C_MEMREAD_RS_ATTEMPTS; ++attempt)
883 last_error = try_repeated_start();
888 mspm0_i2c_recover_controller(res_.instance);
891 for (uint32_t attempt = 0; attempt < MSPM0_I2C_MEMREAD_FALLBACK_ATTEMPTS; ++attempt)
893 last_error = PollingWrite7(ADDR7, addr_bytes, ADDR_SIZE);
897 PollingRead7(ADDR7,
static_cast<uint8_t*
>(read_data.
addr_), read_data.
size_);
903 mspm0_i2c_recover_controller(res_.instance);
906 return finalize(last_error);
只读原始数据视图 / Immutable raw data view
size_t size_
数据字节数 / Data size in bytes
const void * addr_
数据起始地址 / Data start address
I2C(Inter-Integrated Circuit)接口类。 I2C (Inter-Integrated Circuit) interface class.
ErrorCode Read(uint16_t slave_addr, RawData read_data, ReadOperation &op, bool in_isr=false) override
读取 I2C 设备的数据。 Reads data from an I2C device.
ErrorCode MemWrite(uint16_t slave_addr, uint16_t mem_addr, ConstRawData write_data, WriteOperation &op, MemAddrLength mem_addr_size=MemAddrLength::BYTE_8, bool in_isr=false) override
向 I2C 设备指定寄存器写入数据。 Writes data to a specific register of an I2C device.
ErrorCode MemRead(uint16_t slave_addr, uint16_t mem_addr, RawData read_data, ReadOperation &op, MemAddrLength mem_addr_size=MemAddrLength::BYTE_8, bool in_isr=false) override
从 I2C 设备指定寄存器读取数据。 Reads data from a specific register of an I2C device.
ErrorCode SetConfig(Configuration config) override
配置 I2C 设备参数。 Configures the I2C device settings.
ErrorCode Write(uint16_t slave_addr, ConstRawData write_data, WriteOperation &op, bool in_isr=false) override
向 I2C 设备写入数据。 Writes data to an I2C device.
void UpdateStatus(bool in_isr, Status &&status)
按通知方式报告完成结果 / Report completion using the selected mode.
OperationType type
当前通知方式 / Current notification mode.
可写原始数据视图 / Mutable raw data view
size_t size_
数据字节数 / Data size in bytes
void * addr_
数据起始地址 / Data start address
LibXR 命名空间 / LibXR namespace.
ErrorCode
定义错误码枚举 / Defines an enumeration for error codes
@ NOT_SUPPORT
不支持 / Not supported
@ FAILED
操作失败 / Operation failed
@ OK
操作成功 / Operation successful
@ ARG_ERR
参数错误 / Argument error
I2C 设备的配置信息结构体。 Configuration structure for an I2C device.
uint32_t clock_speed
I2C 通信时钟速率(单位:Hz) / The I2C clock speed (in Hz).