libxr
Embedded C++ framework for bare-metal, RTOS and Linux
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ch32_uart_def.hpp
1#pragma once
2
3#include "libxr.hpp"
4#include DEF2STR(LIBXR_CH32_CONFIG_FILE)
5
9typedef enum
10{
11#if defined(USART1)
12 CH32_USART1,
13#endif
14#if defined(USART2)
15 CH32_USART2,
16#endif
17#if defined(USART3)
18 CH32_USART3,
19#endif
20#if defined(USART4)
21 CH32_USART4,
22#endif
23#if defined(USART5)
24 CH32_USART5,
25#endif
26#if defined(USART6)
27 CH32_USART6,
28#endif
29#if defined(USART7)
30 CH32_USART7,
31#endif
32#if defined(USART8)
33 CH32_USART8,
34#endif
35#if defined(UART1)
36 CH32_UART1,
37#endif
38#if defined(UART2)
39 CH32_UART2,
40#endif
41#if defined(UART3)
42 CH32_UART3,
43#endif
44#if defined(UART4)
45 CH32_UART4,
46#endif
47#if defined(UART5)
48 CH32_UART5,
49#endif
50#if defined(UART6)
51 CH32_UART6,
52#endif
53#if defined(UART7)
54 CH32_UART7,
55#endif
56#if defined(UART8)
57 CH32_UART8,
58#endif
59 CH32_UART_NUMBER,
60 CH32_UART_ID_ERROR
61} ch32_uart_id_t;
62
63static constexpr uint8_t CH32_UART_APB_MAP[] = {
64#if defined(USART1)
65 2,
66#endif
67#if defined(USART2)
68 1,
69#endif
70#if defined(USART3)
71 1,
72#endif
73#if defined(USART4)
74 0,
75#endif
76#if defined(USART5)
77 0,
78#endif
79#if defined(USART6)
80 0,
81#endif
82#if defined(USART7)
83 0,
84#endif
85#if defined(USART8)
86 0,
87#endif
88#if defined(UART1)
89 0,
90#endif
91#if defined(UART2)
92 0,
93#endif
94#if defined(UART3)
95 0,
96#endif
97#if defined(UART4)
98 1,
99#endif
100#if defined(UART5)
101 1,
102#endif
103#if defined(UART6)
104 1,
105#endif
106#if defined(UART7)
107 1,
108#endif
109#if defined(UART8)
110 1,
111#endif
112};
113
114static constexpr uint32_t CH32_UART_RCC_PERIPH_MAP[] = {
115#if defined(USART1)
116 RCC_APB2Periph_USART1,
117#endif
118#if defined(USART2)
119 RCC_APB1Periph_USART2,
120#endif
121#if defined(USART3)
122 RCC_APB1Periph_USART3,
123#endif
124#if defined(USART4)
125 0,
126#endif
127#if defined(USART5)
128 0,
129#endif
130#if defined(USART6)
131 0,
132#endif
133#if defined(USART7)
134 0,
135#endif
136#if defined(USART8)
137 0,
138#endif
139#if defined(UART1)
140 0,
141#endif
142#if defined(UART2)
143 0,
144#endif
145#if defined(UART3)
146 0,
147#endif
148#if defined(UART4)
149 RCC_APB1Periph_UART4,
150#endif
151#if defined(UART5)
152 RCC_APB1Periph_UART5,
153#endif
154#if defined(UART6)
155 RCC_APB1Periph_UART6,
156#endif
157#if defined(UART7)
158 RCC_APB1Periph_UART7,
159#endif
160#if defined(UART8)
161 RCC_APB1Periph_UART8,
162#endif
163};
164
165static constexpr uint32_t CH32_UART_RCC_PERIPH_MAP_DMA[] = {
166#if defined(USART1)
167 RCC_AHBPeriph_DMA1,
168#endif
169#if defined(USART2)
170 RCC_AHBPeriph_DMA1,
171#endif
172#if defined(USART3)
173 RCC_AHBPeriph_DMA1,
174#endif
175#if defined(USART4)
176 RCC_AHBPeriph_DMA1,
177#endif
178#if defined(USART5)
179 RCC_AHBPeriph_DMA1,
180#endif
181#if defined(USART6)
182 RCC_AHBPeriph_DMA1,
183#endif
184#if defined(USART7)
185 RCC_AHBPeriph_DMA1,
186#endif
187#if defined(USART8)
188 RCC_AHBPeriph_DMA1,
189#endif
190#if defined(UART1)
191 RCC_AHBPeriph_DMA2,
192#endif
193#if defined(UART2)
194 RCC_AHBPeriph_DMA2,
195#endif
196#if defined(UART3)
197 RCC_AHBPeriph_DMA2,
198#endif
199#if defined(UART4)
200#if defined(CH32V20x_D6) || defined(CH32V20x_D8) || defined(CH32V20x_D8W)
201 RCC_AHBPeriph_DMA1,
202#else
203 RCC_AHBPeriph_DMA2,
204#endif
205#endif
206#if defined(UART5)
207 RCC_AHBPeriph_DMA2,
208#endif
209#if defined(UART6)
210 RCC_AHBPeriph_DMA2,
211#endif
212#if defined(UART7)
213 RCC_AHBPeriph_DMA2,
214#endif
215#if defined(UART8)
216 RCC_AHBPeriph_DMA2,
217#endif
218};
219
220static constexpr uint32_t CH32_UART_TX_DMA_IT_MAP[] = {
221#if defined(USART1)
222 DMA1_IT_TC4,
223#endif
224#if defined(USART2)
225 DMA1_IT_TC7,
226#endif
227#if defined(USART3)
228 DMA1_IT_TC2,
229#endif
230#if defined(USART4)
231 0,
232#endif
233#if defined(USART5)
234 0,
235#endif
236#if defined(USART6)
237 0,
238#endif
239#if defined(USART7)
240 0,
241#endif
242#if defined(USART8)
243 0,
244#endif
245#if defined(UART1)
246 0,
247#endif
248#if defined(UART2)
249 0,
250#endif
251#if defined(UART3)
252 0,
253#endif
254#if defined(UART4)
255#if !(defined(CH32V20x_D6) || defined(CH32V20x_D8) || defined(CH32V20x_D8W)) && \
256 defined(DMA2_IT_TC5)
257 DMA2_IT_TC5,
258#else
259 DMA1_IT_TC1,
260#endif
261#endif
262#if defined(UART5)
263 DMA2_IT_TC4,
264#endif
265#if defined(UART6)
266 DMA2_IT_TC6,
267#endif
268#if defined(UART7)
269 DMA2_IT_TC8,
270#endif
271#if defined(UART8)
272 DMA2_IT_TC10,
273#endif
274};
275
276static constexpr uint32_t CH32_UART_RX_DMA_IT_TC_MAP[] = {
277#if defined(USART1)
278 DMA1_IT_TC5,
279#endif
280#if defined(USART2)
281 DMA1_IT_TC6,
282#endif
283#if defined(USART3)
284 DMA1_IT_TC3,
285#endif
286#if defined(USART4)
287 0,
288#endif
289#if defined(USART5)
290 0,
291#endif
292#if defined(USART6)
293 0,
294#endif
295#if defined(USART7)
296 0,
297#endif
298#if defined(USART8)
299 0,
300#endif
301#if defined(UART1)
302 0,
303#endif
304#if defined(UART2)
305 0,
306#endif
307#if defined(UART3)
308 0,
309#endif
310#if defined(UART4)
311#if !(defined(CH32V20x_D6) || defined(CH32V20x_D8) || defined(CH32V20x_D8W)) && \
312 defined(DMA2_IT_TC3)
313 DMA2_IT_TC3,
314#else
315 DMA1_IT_TC8,
316#endif
317#endif
318#if defined(UART5)
319 DMA2_IT_TC2,
320#endif
321#if defined(UART6)
322 DMA2_IT_TC7,
323#endif
324#if defined(UART7)
325 DMA2_IT_TC9,
326#endif
327#if defined(UART8)
328 DMA2_IT_TC11,
329#endif
330};
331
332static constexpr uint32_t CH32_UART_RX_DMA_IT_HT_MAP[] = {
333#if defined(USART1)
334 DMA1_IT_HT5,
335#endif
336#if defined(USART2)
337 DMA1_IT_HT6,
338#endif
339#if defined(USART3)
340 DMA1_IT_HT3,
341#endif
342#if defined(USART4)
343 0,
344#endif
345#if defined(USART5)
346 0,
347#endif
348#if defined(USART6)
349 0,
350#endif
351#if defined(USART7)
352 0,
353#endif
354#if defined(USART8)
355 0,
356#endif
357#if defined(UART1)
358 0,
359#endif
360#if defined(UART2)
361 0,
362#endif
363#if defined(UART3)
364 0,
365#endif
366#if defined(UART4)
367#if !(defined(CH32V20x_D6) || defined(CH32V20x_D8) || defined(CH32V20x_D8W)) && \
368 defined(DMA2_IT_HT3)
369 DMA2_IT_HT3,
370#else
371 DMA1_IT_HT8,
372#endif
373#endif
374#if defined(UART5)
375 DMA2_IT_HT2,
376#endif
377#if defined(UART6)
378 DMA2_IT_HT7,
379#endif
380#if defined(UART7)
381 DMA2_IT_HT9,
382#endif
383#if defined(UART8)
384 DMA2_IT_HT11,
385#endif
386};
387
388static DMA_Channel_TypeDef* const CH32_UART_TX_DMA_CHANNEL_MAP[] = {
389#if defined(USART1)
390 DMA1_Channel4,
391#endif
392#if defined(USART2)
393 DMA1_Channel7,
394#endif
395#if defined(USART3)
396 DMA1_Channel2,
397#endif
398#if defined(USART4)
399 nullptr,
400#endif
401#if defined(USART5)
402 nullptr,
403#endif
404#if defined(USART6)
405 nullptr,
406#endif
407#if defined(USART7)
408 nullptr,
409#endif
410#if defined(USART8)
411 nullptr,
412#endif
413#if defined(UART1)
414 NULL,
415#endif
416#if defined(UART2)
417 NULL,
418#endif
419#if defined(UART3)
420 NULL,
421#endif
422#if defined(UART4)
423#if !(defined(CH32V20x_D6) || defined(CH32V20x_D8) || defined(CH32V20x_D8W)) && \
424 defined(DMA2_Channel5)
425 DMA2_Channel5,
426#else
427 DMA1_Channel1,
428#endif
429#endif
430#if defined(UART5)
431 DMA2_Channel4,
432#endif
433#if defined(UART6)
434 DMA2_Channel6,
435#endif
436#if defined(UART7)
437 DMA2_Channel8,
438#endif
439#if defined(UART8)
440 DMA2_Channel10,
441#endif
442};
443
444static DMA_Channel_TypeDef* const CH32_UART_RX_DMA_CHANNEL_MAP[] = {
445#if defined(USART1)
446 DMA1_Channel5,
447#endif
448#if defined(USART2)
449 DMA1_Channel6,
450#endif
451#if defined(USART3)
452 DMA1_Channel3,
453#endif
454#if defined(USART4)
455 nullptr,
456#endif
457#if defined(USART5)
458 nullptr,
459#endif
460#if defined(USART6)
461 nullptr,
462#endif
463#if defined(USART7)
464 nullptr,
465#endif
466#if defined(USART8)
467 nullptr,
468#endif
469#if defined(UART1)
470 NULL,
471#endif
472#if defined(UART2)
473 NULL,
474#endif
475#if defined(UART3)
476 NULL,
477#endif
478#if defined(UART4)
479#if !(defined(CH32V20x_D6) || defined(CH32V20x_D8) || defined(CH32V20x_D8W)) && \
480 defined(DMA2_Channel3)
481 DMA2_Channel3,
482#else
483 DMA1_Channel8,
484#endif
485#endif
486#if defined(UART5)
487 DMA2_Channel2,
488#endif
489#if defined(UART6)
490 DMA2_Channel7,
491#endif
492#if defined(UART7)
493 DMA2_Channel9,
494#endif
495#if defined(UART8)
496 DMA2_Channel11,
497#endif
498};
499
500static constexpr IRQn_Type CH32_UART_IRQ_MAP[] = {
501#if defined(USART1)
502 USART1_IRQn,
503#endif
504#if defined(USART2)
505 USART2_IRQn,
506#endif
507#if defined(USART3)
508 USART3_IRQn,
509#endif
510#if defined(USART4)
511 USART4_IRQn,
512#endif
513#if defined(USART5)
514 USART5_IRQn,
515#endif
516#if defined(USART6)
517 USART6_IRQn,
518#endif
519#if defined(USART7)
520 USART7_IRQn,
521#endif
522#if defined(USART8)
523 USART8_IRQn,
524#endif
525#if defined(UART1)
526 UART1_IRQn,
527#endif
528#if defined(UART2)
529 UART2_IRQn,
530#endif
531#if defined(UART3)
532 UART3_IRQn,
533#endif
534#if defined(UART4)
535 UART4_IRQn,
536#endif
537#if defined(UART5)
538 UART5_IRQn,
539#endif
540#if defined(UART6)
541 UART6_IRQn,
542#endif
543#if defined(UART7)
544 UART7_IRQn,
545#endif
546#if defined(UART8)
547 UART8_IRQn,
548#endif
549};
550
551ch32_uart_id_t ch32_uart_get_id(USART_TypeDef* addr);
552USART_TypeDef* ch32_uart_get_instance_id(ch32_uart_id_t);